Steps in the Verification of an Occam-to-FPGA Compiler
نویسندگان
چکیده
This paper reports on the progress made in developing techniques for the verification of an Occam to FPGA compiler. Communicating Sequential Processes (CSP) has been used to model the circuits generated by our compiler. This CSP has then been subjected to tests for deadlock and livelock freedom using the Failures-Divergence Refinement tool (FDR, [6]). In addition, FDR has been used to prove that the circuits emitted have behaviours equivalent to CSP specifications of the original Occam source codes. Ke ywords: FPGA, Occam, CSP, logic synthesis, embedded systems
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